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San Francisco, CA, United States

Company Profile

Senior Member Technical Staff


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San Francisco, CA, United States 


Analytics, AWS - Amazon Web Service, Big Data Analytics, Big Data Architect, Big Data Trainer, Business Development, C++ #, 706, Data Scientist, Hadoop, Hadoop ADMIN, Java Developer, Machine Learning, 741

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Job Description:

  • evelopment, maintenance and testing of software emulation-related products, including development of accurate C/C++ models of CPUs and typical devices that make up a modern day System-on-Chip (SoC).
    Acquire and maintain knowledge of our current tools, languages, and processes as deemed necessary to support design, implementation, and release of current and future software products and features
    Bringing up of the latest versions of Linux and Android software on SoC models, development of Verilog test benches and integrating the SoC models with the rest of the HW descriptions of the customers product
    Development of Verilog code to extract architecturally important state of CPUs from RTL based CPU emulation runs
    Participate in product development projects including specifications, design, scheduling, code reviews and inspections, implementation, testing, documentation and product maintenance, so that schedules and releases are predictable and measurable against project objectives and goals

Job Requirements:

  • 0-5 years of experience in software development, preferable in C, C++ and on Linux environment
    Good analytical, problem solving and debugging skills with exposure to product development life cycle
    Good understanding of data structures and Algorithms
    Knowledge of CPU/ Processor Architecture
    Exposure to product development life cycle
    Familiarity with scripting languages like awk, perl, tcl, python
    Self-motivated and able to work independently
    Good communication skills to work with management, colleagues and other teams
    Would be great to have:
    Knowledge of/exposure to assembly languages, ARM processors architecture, Verilog, SystemC and functional verification tools like ModelSim
    Experience with writing synthesizable RTL in Verilog/VHDL

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